module pc(
        input  ld_pc,
        input  in_pc,
        input  clk,
        input  [7:0]a,
        output reg [7:0]c
        );
initial c=8'b00000000;
always@(negedge clk)
begin
    if( in_pc==1 && ld_pc==0 ) c <= c+1'b1;
    else if( in_pc==0 && ld_pc==1 )  c<=a;
    else ;
end
endmodule         